Design and Performance Evaluation of a High-Speed VLSI Router Using Efficient Buffering Techniques

This paper presents the design and performance evaluation of a high-speed VLSI router optimized using advanced buffering techniques. As on-chip communication demands increase in modern System-on-Chip (SoC) architectures, efficient router design becomes critical for achieving low latency and high throughput. The proposed router architecture incorporates input buffering and virtual channel buffering to reduce congestion and improve data flow efficiency. The design is implemented using VLSI design principles and evaluated based on key performance metrics such as latency, throughput, area, and power consumption. Simulation results demonstrate that the proposed buffering techniques significantly enhance router performance compared to conventional designs, making it suitable for high-speed Network-on-Chip (NoC) applications.