An Energy-Efficient Cryogenic Readout Front-End Achieving 2.85 zJ·A FoM at 4 K for Spin Qubits

This paper presents a 65-nm CMOS cryogenic DC readout circuit for spin qubits that employs a charge-sampling front-end, mitigating the dominant static power consumption by replacing the conventional second-stage operational amplifier with a low-power floating-inverter amplifier (FIA). Designed in a 65-nm CMOS process, the circuit operates at 4 K and consumes only 5.7 μW under a 1.2 V supply, a 73% reduction compared to the conventional op-amp-based design. The core circuit occupies a compact 0.007 mm^2 area. Post-layout simulations verify a current resolution of 50 pA in 10 μs readout time, achieving a Figure-of-Merit (FoM) of 2.85 zJ·A. These results confirm the effectiveness and scalability of the proposed architecture as a competitive solution for dense, multi-qubit readout arrays.