Fast, Explainable Surrogate Models for gem5 Cache Design Space Exploration

Cycle-accurate simulators such as gem5 are indispensable for microarchitecture design, but their runtime makes large-scale design-space exploration (DSE) expensive and environmentally costly. We present a practical, explainable surrogate modeling pipeline that replaces most gem5 cache simulations with physically constrained machine-learning models trained on a structured dataset of ~15,000 validated gem5 runs. Using gem5's Syscall Emulation (SE) mode and six diverse workloads (crc32, dijkstra, fft, matrix_mul, qsort, sha), we train monotonicity-constrained XGBoost regressors to predict IPC and L2 miss rate from cache parameters. The resulting models achieve on held-out test sets and retain strong accuracy on a 26-configuration out-of-distribution (OOD) stress test while accelerating evaluation by up to ~800× on the critical simulation path. We release all trained models, SHAP explainability artifacts, and code via HuggingFace and GitHub to enable reproducible and interpretable architecture exploration.