An area and power efficient 16-channel neural signal processor IC with Δ-Σ operator for wireless brain-machine-interface applications

Area and power efficient on-chip neural spike detection and compression technology is a key enabler for high channel count wireless neural recording system. This paper proposed a Δ-Σ operator for the first time to perform spike detection, achieving both lower area and lower power consumption, compared with the conventional NEO operator. A pipeline architecture with shared hardware resources is also designed based on the similarities between Δ-Σ operator and the first- and second-order difference extrema (FSDE) feature extraction algorithm, which further reduces the silicon area and power consumption. A 16-channel neural signal processor (NSP) prototype IC was designed and implemented in a standard 180nm CMOS process to validate the proposed Δ-Σ operator and pipeline architecture. Measurement results show that the proposed NSP achieves a detection accuracy of 93.9%, with silicon area of 0.044 mm²/ch and power consumption of 1.35 μW/ch.