Resource‑Optimized ω‑K Algorithm‑Based FPGA On‑Board SAR Processor: Design and Validation

Recent advances in SAR constellation missions are expected to increase revisit frequency and data volume, potentially constraining conventional ground based image processing due to end to end latency and downlink bandwidth limitations. On board SAR processing is therefore regarded as a viable solution; however, CPU/GPU based systems are unsuitable for low power, radiation hardened space environments. This study describes an FPGA based onboard SAR processor implementing a resource optimized Omega K algorithm to efficiently convert raw strip map data into a 65,536 × 65,536 single look complex (SLC) and geocoded ellipsoid corrected (GEC) images within approximately 200 seconds. The proposed approach offers resource efficient trade offs and practical implementability by avoiding resource intensive operations such as Stolt interpolation and two dimensional FFTs. Validation using real satellite data demonstrates the feasibility of energy efficient and high speed onboard SAR processing, highlighting its role as a key enabler for next generation space missions in disaster response, environmental monitoring, and national security.