Drafting and Multi-Input Switching in Digital Dynamic Timing Simulation for Multi-Input Gates

Trace-history-dependent effects such as drafting and multi-input switching are poorly modeled in static timing analysis, yet do not justify excessive transistor-level analog simulations. We present a closed-form analytic delay model for fast digital dynamic timing analysis of interconnected NOR gates, which captures both effects. Our delay formulas are derived from a thresholded hybrid gate model based on non-constant-coefficient differential equations, which can be analytically parametrized via a few characteristic gate delay values. By utilizing our formulas in the discrete-event simulator-based Involution Tool, we show that accurate circuit simulation can be done at roughly inertial-delay cost. The significantly improved timing prediction accuracy of our delay model is demonstrated by two representative benchmark circuits.