From Pilot To HVM: A Practical Overlay Yield Prediction Workflow For FOPLP Lithography

As the AI market continues to expand rapidly, the challenge lies in how to swiftly transition to mass production for market demand. Yield control is another major topic. AI chips integrate multiple control units and high-bandwidth memory (HBM) during the packaging process. These components are expensive. Therefore, maximizing yield at every step and identifying defects early to minimize losses is critical. Yield prediction technology addresses both the speed ramp up and overlay yield control of FOPLP lithography. This approach utilizes an offline metrology tool to measure die shifts or pattern distortions on the panel substrate. The metrology data are then analyzed using machine learning algorithms, which, when combined with customized process parameters, can accurately predict overlay errors and overlay yield. This predictive insight allows for more informed decision-making and earlier intervention in the lithography process.