A 28 Nm 37.2 TFLOPS/W Word-Alignment Pipeline Floating-Point CIM Macro for CNN-Training and Diffusion Models

Recent advances in generative AI and large-scale neural networks have drastically increased computational and memory bandwidth demands, exacerbating the classic von Neumann memory wall. Computing-in-memory (CIM) has emerged as a promising remedy by collocating storage and MAC operations inside memory arrays. Meanwhile, floating-point (FP) CIM is attracting growing interest for training and diffusion models, but most existing designs rely on coarse group-alignment of exponents, incurring quantization and accumulation errors that prevent deployment in high-accuracy workloads. This work presents a 28 nm word-alignment FP-CIM macro with a four-stage MAC pipeline that supports CNN training and diffusion models. The macro integrates three key techniques: (1) a word-aligned FP MAC flow with pipelined exponent comparison, mantissa shift, and partial-sum accumulation; (2) a low-bit-skip Wallace-tree BF16 multiplier that removes negligible partial products to improve power, area, and speed; and (3) a DFF-based double-function shift unit with a replica-clock scheme for low-latency and PVT-robust barrel shifting. Fabricated in 28 nm CMOS, the 16 Kb macro operates from 0.45–0.9 V and achieves 37.2 TFLOPS/W at 0.45 V and 2.56 TFLOPS/mm$^{2}$at 0.9 V. Chip-level demonstrations obtain 72.96% top-1 on VGG16/CIFAR100, 76.14% on ResNet18/ImageNet, 57.95% mAP on YOLOv8/COCO, and 10.57 FID on a CelebA diffusion model, all within 0.34% of FP32 baselines. Overall, the proposed word-aligned FP-CIM improves the energy–area–accuracy figure of merit by 8.23–26.15× over prior FP-CIM macros.