Ion Beam Etching as a Disruptive Integration Strategy for Advanced Logic: From T2T Scaling to Tilted 3D-IC Routing

View at publisher
Authors: Jongsoon Park, Keun Hee Bai, Hyonwook Ra, Seongho Son, Seongjun Hong, Back Kyu Choi, 김성택, Yun Jae Park, K. S. Kim, Sunjung Kim, Jong Woo Hong, Sunghyun Kim
+4 more Jong Myeong Lee, Jaihyuk Song, Jongchul Park, Geun Young Yeom
Cited by: 0
References: 4

Abstract

ABSTRACT As semiconductor scaling reaches the 1.4nm node and beyond, extreme ultraviolet (EUV) lithography faces critical cost and physical constraints, particularly the tip-to-tip (T2T) spacing bottleneck. To address these challenges, we evaluate directional ion-beam etching (IBE) as a disruptive 3D patterning strategy to enable T2T shrinkage without additional EUV cut masks. We compare two distinct IBE architectures (that is, Grid and Ribbon Beam Systems) and it is found that, Ribbon Beam System showed better angle control characteristics and, for the Ribbon Beam System, precise angular control of the ion beam allows for a Y/X etch selectivity exceeding 10:1 in 42nm back end of line (BEOL) patterns. This directional selectivity is further utilized to propose a novel 3D-IC interconnect strategy: tilted routing. By departing from traditional orthogonal coordinates and adopting diagonal routing paths inspired by IBE ion trajectories, we demonstrate the potential to eliminate up to four EUV-patterned layers (Via1/2, M2/3) in optimized logic structures. The feasibility of this approach has been validated on a 42nm pitch BEOL pattern, confirming targeted critical dimension (CD) modulation and successful integration. From a manufacturing perspective, the proposed IBE-based integration can deliver a reduction of 30 auxiliary process steps, resulting in estimated cost savings of approximately $30 million per 10,000 wafers. These results establish IBE-enabled tilted routing as a scalable and cost-effective solution for next-generation 3D-IC architectures, offering a viable pathway to extend scaling trends beyond the limits of conventional EUV lithography.

Fields of Study & Subjects

Advancements in Photolithography Techniques 3D IC and TSV technologies Copper Interconnects and Reliability

Publication details

Journal / source
Pan Pacific Symposium
Volume
29
Issue
1
Pages
81–86
Publication date
1 February 2026
Language
EN