RISC-V Soft-IP Cores for Custom Avionics System Design

The growing complexity of avionics systems requires a shift toward customized design approaches to meet strict safety and reliability requirements. Currently, there are no modern processor architectures with sufficiently well-understood and controllable internal functionality that are suitable for use in avionics systems and certifiable to a high DAL. This paper explores the use of reconfigurable avionics computing architectures for custom multi-core processor designs for avionics applications. Our research demonstrates how modular processing units can be tailored for a safety-critical avionics application by developing and evaluating a custom RISC-V soft-IP multi-core architecture. Leveraging the open nature of the RISC-V instruction-set architecture, the proposed design allows for architectural customizations, improved determinism, and mitigation of multi-core interference by eliminating shared caches and memory. Implemented on a FPGA, it supports the instantiation of multiple cores, as well as efficient inter-processor communication via message queues, semaphores, and replicated scratchpad memory. We validated the multi-core concept using a helicopter flight control algorithm in a HIL simulation. This approach reduced the execution time by 44% compared to a single-core setup while maintaining timing determinism. Overall, this research highlights the potential of soft-IP technology to advance the development of modular, customized avionics computing systems.