CONTACT AND INTERFACE STUDY OF MONOLAYER TRANSITION METAL DICHALCOGENIDES TRANSISTORS

Monolayer (ML) transition metal dichalcogenides (TMDs) have emerged as promising channel materials for future transistors due to their atomically thin geometry, enabling aggressive channel length scaling. Their short electrostatic screening length, sizable bandgap, and high carrier mobility make ML TMDs strong candidates for advanced technology nodes. This thesis presents several key advancements that demonstrate the potential of ML TMD transistors based on statistical performance evaluation. First, we fabricated double-gated monolayer WS2 field-effect transistors (FETs) with a 30 nm channel length, achieving excellent performance, a drive current of 400 µA/µm. Technology Computer-Aided Design (TCAD) simulations were employed to optimize the device structure by introducing an air-gap spacer between the source and top gate, which effectively suppressed off-state degradation and mitigated negative threshold voltage shifts. Second, we significantly reduced contact resistance in ML MoS2 FETs by using conventional metal, Nickle, bringing it down to approximately 500 Ω·µm through contact interface engineering. Lastly, we developed a contact strategy using metallic Nb0.3W0.7Se2 as a contact for monolayer and bilayer WSe2 transistors with channel lengths down to 100 nm, the resulting 2D/2D contacted FETs exhibit high on-current densities of up to 375 µA/µm and 1.1 mA/µm on monolayer and bilayer WSe2 channels, respectively.The pristine, dangling-bond-free nature of monolayer (ML) transition metal dichalcogenides (TMDs) poses a significant challenge for top dielectric formation, which is a key element in enhancing electrical performance. Two different methods have been introduced in this thesis for forming interfacial layers to enable the successful growth of top dielectrics. The first approach involves the formation of a physical metal oxide layer via the natural oxidation of pre-deposited metal atoms. By utilizing a pre-deposited Aluminum seeding layer, an ML WS2 transistor exhibiting an ideal subthreshold slope of approximately 63 mV/dec has been demonstrated. The second method integrates amorphous boron nitride (aBN), grown at 250◦C, achieving a seeding-layer-free process for fabricating double-gated field-effect transistors (FETs). This integration results in a low interface trap density of less than 1012 cm−2 and an ideal subthreshold slope of around 60 mV/dec over a two-order current range (10-4 to 10-6 µA/µm). Furthermore, we investigated the interface trapped density landscape of ML MoS2, a temperature dependent properties of ML MoS2. Due to its inherent two-valley degeneracy and reduced phonon scattering, the mobility versus carrier density exhibits a gentler slope near −1, compared to −1.5 in multilayer MoS2. Notably, ML MoS2 shows a dielectric-constant-independent mobility behavior, with an extracted mobility in the range of 45 to 55 cm2/V·s.We also demonstrated the first on-chip P-bit core by integrating a P-bit with ML MoS2 transistors. The low processing temperature of ML MoS2 FETs enables their fabrication alongside probabilistic magnetic tunnel junctions (MTJs) without degrading MTJ performance. The high on-current of ML MoS2 allows for effective resistance matching between the MTJs and input resistance, which is critical for the performance of the P-bit core.