Parallel targeted simulation for timing verification of digital circuits

Stanford Digital Repository 2026 Thesis Open access

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Authors: Rajsekhar Setaluri, Pat Hanrahan, Mark Horowitz, Christopher Torng, Stanford University. School of Engineering., Stanford University. Computer Science Department.
DOI: 10.25740/cj099sp2434
Cited by: 0

Fields of Study & Subjects

Formal Methods in Verification VLSI and FPGA Design Techniques Low-power high-performance VLSI design

Publication details

Journal / source
Stanford Digital Repository
Publication date
11 March 2026
Language
EN
Document type
Thesis