Research towards low power trainable neuromorphic integrated circuits

In today’s world, the number of applications incorporating Artificial Intelligence (AI) is ever increasing. This rapid expansion of AI has led to the blistering demands of faster, more complex hardware and energy requirements, raising significant infrastructure concerns. Among the various models of AI, Neural Networks (NN) are one of the most prominent and widely adopted concepts, promising great modeling capabilities and generalization performance, yet being computationally intensive. To address these issues, research is directed towards alternative, more energy efficient implementations of Neural Networks, such as Analog Neural Networks and Neuromorphic systems. Neuromorphic Networks (NN) are a biologically-inspired, hardware-based type of Neural Network, where the network’s data are inscribed directly in the circuit and information is encoded in physical quantities such as voltage, current, and conductance. In this work, an analog implementation of a single hidden layer NN in 22nm 0.8V FDSOI technology was studied, adapting the design of the previously proposed Trainable Analog Block (TAB), originally fabricated in 65nm bulk CMOS. For the development of the network circuits such as current mirrors, M-2M ladders, D/A Converters and operational amplifiers, had to be modified accordingly, with some of these realizations not yet reported in the literature for the FDSOI technology. A maximum power consumption of 240nW per neuron and output-weight block was achieved, while maintaining robust and accurate performance.