EFFICIENT FPGA REALIZATION OF LIGHTWEIGHT AES FOR LOW-POWER IOT SECURITY SYSTEMS

Background: The growing need for secure communication on resource-constrained systems, such as those in the Internet of Things (IoT), has led to a significant increase in demand for lightweight symmetric ciphers. Nevertheless, different techniques and implementations exist, making the selection of the optimal security solution for a particular application challenging. Objective: This study primarily focuses on implementing an optimised Lightweight Advanced Encryption Standard (LAES) algorithm in hardware to address the critical need for energy-efficient security solutions for IoT devices. Methods: This study implements LAES to meet the security requirements for IoT devices. The Kintex 7 and Spartan 7 FPGAs (Field Programmable Gate Arrays) are utilised for implementation, with critical performance metrics such as hardware area utilisation used to evaluate performance. The algorithm eliminates the computationally expensive MixColumns operation from standard AES while maintaining essential security transformations. Performance evaluation focused on hardware resource utilisation (LUTs, FFs, IO) and power consumption across clock frequencies ranging from 1 ns to 20 ns. Results: The results indicate significant advancements in achieving area and power-efficient designs. Our findings show that the reduction in power consumption is by 95.29% and 92.07% as compared to existing models. The area consumption, such as LUTs, FFs, and IO, has also been significantly decreased compared to existing models. Conclusions: The proposed LAES architecture demonstrates that strategic algorithm optimisation can yield substantial improvements in both power efficiency and hardware utilisation without compromising security, making it highly suitable for IoT deployment.