Edge-Optimized Neuromorphic VLSI Accelerator Based On Hybrid Spiking Neural Models

The rapid proliferation of edge intelligence has created an urgent demand for ultra-low-power, high-performance hardware accelerators capable of executing complex AI workloads under stringent energy and latency constraints. This paper presents an edge-optimized neuromorphic VLSI accelerator based on hybrid spiking neural models, specifically designed to support real-time inference in resource-constrained edge environments. The proposed architecture integrates biologically inspired spiking neurons with conventional artificial neural processing units, enabling efficient event-driven computation and adaptive learning capabilities. A hybrid processing framework is introduced, combining rate-coded and temporal spiking mechanisms to enhance representational efficiency and inference accuracy while minimizing memory access overhead. The accelerator employs parallel spike routing, on-chip synaptic weight storage, and dynamic voltage-frequency scaling to achieve optimal energy efficiency. Hardware-aware optimizations, including sparsity exploitation and spike-driven computation scheduling, significantly reduce switching activity and power consumption. Post-layout simulations using a 45-nm CMOS technology demonstrate up to 62% reduction in power consumption and 1.8× improvement in throughput compared to conventional digital CNN accelerators. Experimental evaluation on benchmark datasets confirms competitive accuracy while achieving sub-millijoule energy per inference. The proposed design establishes a scalable and energy-efficient neuromorphic VLSI framework, making it highly suitable for next-generation edge AI applications such as IoT sensing, wearable devices, and autonomous systems.