A Differentiated Process for 4H-SiC MOS Interface Defect Control and Performance Comparison with OP-ROA/RPA

This study focuses on solving longstanding challenges of hightemperature semiconductor cleaning techniques.These methods often struggle to balance three key goals: effective oxide removal, defect control, and preservation of substrate integrity.Issues like excessive thermal stress causing substrate warpage and uneven oxide layer etching have long limited their scalability.Specifically, the research examines how two critical problems disrupt interface electronic behavior: residual carbon atoms left unreacted during high-temperature processes, and oxide defects such as oxygen vacancies or Si-O-C bonds.These impurities raise carrier trapping probability, reduce charge mobility, and ultimately degrade device performance-especially in high-power or high-frequency applications.To tackle these issues, the study uses state-of-the-art characterization tools: high-frequency capacitance-voltage (C-V) profiling to quantify interface trap dynamics, positron annihilation lifetime spectroscopy (PAT/PNT) to detect sub-nanoscale defects, secondary ion mass spectroscopy (SIMS) for atomic-level elemental depth mapping, and ramp-JE testing to evaluate oxide layer breakdown strength.Rigorous experiments show the optimized cleaning methods deliver significant improvements: they not only remove oxide more thoroughly and uniformly but also sharply reduce Dit (interfacial defect concentration), a key metric for interface quality.Additionally, the study tests device stability and reliability under harsh conditions-including high temperatures up to 200° C and voltage stress cycles-to validate long-term performance.