Amygdalic Decision Architecture for Embedded AI Systems

This paper describes a hardware architecture that moves AI safety constraints out of software and into circuit topology — and analyzes the cost inversion that makes this viable on sub-$15 NPU hardware. A distilled vision model, structured as N parallel narrow classifiers, replaces the vision-detectable subset of conventional discrete sensor arrays at significantly lower bill-of-materials cost. Classifier outputs are routed to a dedicated hardware node — the amygdala circuit — implemented as a sparse FPGA-based lookup table that maps perception state to one element of a pre-wired actuator option set O. The resulting guarantee is precisely stated: the actuator command space is deterministically bounded by circuit topology regardless of inference-layer behavior, under the assumption that the FPGA and communication bus function correctly. This is not a claim that selected actions are always correct; it is a claim that no action outside O is physically reachable. We show this distinction is structurally compatible with hardware certification frameworks (IEC 61508, DO-178C, IEC 62304) in a way that software-only AI systems are not, and analyze the cost inversion that makes deployment viable at scale. Open implementation questions regarding sparse LUT construction, confidence propagation, DAG guarantee extension, and option-set governance are stated precisely.