FPGA implementation of a chaotic attractor based on the structure with negative resistance using a modified ANISHCHENKO-ASTAKHOV model

The article presents a simple and reproducible hardware implementation of a chaotic attractor based on a structure with negative resistance implemented using a modified Anishchenko–Astakhov model on an FPGA with single-cycle integration by the Euler method. At the preparation stage, Python modeling was performed to select parameters and an integration step that ensure a stable chaotic regime. Nonlinearities of the model of a chaotic attractor based on a structure with negative resistance were hardware-accounted for. The system clock of 50 MHz is divided into working 5 MHz, which corresponds to the long critical path of the combinatorial circuit and simplifies timing-closure for educational and demonstration purposes. Comparison of hardware samples with the reference software model confirmed characteristic phase portraits, stable update latency, and preservation of chaotic properties at the declared frequencies. The proposed architecture serves as a “baseline” for further acceleration: partial pipeline of individual operations, increasing bit depth and transition to higher-order methods, as well as for integration with real-time data acquisition interfaces.