ОБГРУНТУВАННЯ ВИБОРУ СТРУКТУРИ АЦП ДЛЯ ПІДВИЩЕННЯ ТОЧНОСТІ СИСТЕМ АВТОМАТИЗАЦІЇ КОНТРОЛЮ ТИСКУ

This article is dedicated to the research of methods for enhancing both the energy efficiency and the high-resolution capabilities of Switched-Capacitor (SC) Delta-Sigma (ΔΣ) Analog-to-Digital Converters (ADCs). It is also analyzed and justified why this architecture is chosen for further research. This is achieved by leveraging novel low-power CMOS circuit design techniques, specifically in scaled CMOS technologies. The priorities are high circuit performance, robustness, low manufacturing costs, and a simple design architecture that can be readily reused by the scientific community for validation and further development. The Delta-Sigma architecture was chosen for its inherent simplicity and high tolerance to major analog block non-idealities, such as op-amp finite gain and comparator offsets. The presented study uses switched-capacitor techniques as the core implementation to achieve high-precision matching between devices, resulting in a performance dependency that relies primarily on the external clock jitter rather than absolute component values. The developed low-current analog circuit methods are aimed at maximizing energy efficiency, taking advantage of the weak and moderate inversion regions of MOS transistor operation to optimize transconductance efficiency (gm/ID). New Class-AB operational amplifiers are also explored as active elements that use energy primarily for dynamic transitions, thus reducing static power consumption at the circuit level. Circuits that are not actively used during a certain period of time are dynamically powered down (power-gated), thus reducing overall power consumption at the system level and minimizing the number of switching devices in the critical signal path. Circuit reliability is improved by deliberately avoiding bootstrapping or other methods that could increase the operating voltage above the nominal power supply. This design choice prevents oxide overstress and enhances the long-term reliability of the target CMOS technology. The study also examines circuit topologies that remain relatively stable across process and temperature variations. Increased stability means better manufacturing yield and fewer inconsistencies between simulated and measured results. Taken together, these design decisions allow the converter to achieve better precision and efficiency without resorting to complex timing schemes, background calibration, or digital post-processing. This makes the proposed techniques suitable for a variety of intelligent sensor systems, including pressure and temperature measurement applications.