A Novel Verification System for Image Algorithm IP Core Testing

To address inefficiency of IP core testing in System-on-Chip (SoC) design, this paper proposes a multimodal integrated testing approach based on FPGA heterogeneous computing. Centered on the ZYNQ platform, the system establishes a collaborative verification framework integrating that combines software simulation with physical testing. The ARM processor runs a ported Linux operating system integrated with OpenCV integration to generate standard test datasets, swhile the bare-metal layer facilitates real-time control of IP cores and acquisition of physical circuit data. Vivado HLS optimization strategies are applied to generate RTL code, and the AXI bus facilitates hardware acceleration and data exchange. Experimental results demonstrate that the optimized matrix multiplication IP core achieves a 27 × speedup, and the corner detection algorithm attains a 3.22 × acceleration. The proposed system offers quantitative insights for IP core optimization strategy selection, enhances verification efficiency supports engineering practicality, and significantly reducing the chip development cycle.