Estimating the Layout Area of Tile-Based FPGAs in Planar and FinFET Technologies

Given the importance of layout area in determining the overall efficiency of any proposed FPGA architecture, it is critical to validate the accuracy of frequently used FPGA area estimation models. The VPR and COFFE area models are two popular models for estimating the layout area of tile-based FPGAs in planar technologies. Both of these models are based on the active area of layouts and do not account for metal area. This can result in area misprediction. This misprediction can be particularly severe for switch blocks, whose metal area grows quadratically while active area grows linearly as a function of their capacity. Therefore, in this work, we first validate the accuracy of the VPR and COFFE area models for FPGA switch blocks in planar technologies by quantifying their errors using the SCMOS design rules. Since the layout technologies have shifted from planar to FinFET technologies, a new FinFET-based area estimation model is needed to accurately predict layout area. In the second part of this work, we propose a new area estimation model that is based on the active area of FinFET layouts. The new model can be used for estimating the layout area of the tile-based FPGAs that are dominated by the active area. The effects of the new features of FinFET, such as dummy gates and fin numbers, are considered. We found the prediction errors of the new model range from 4.6% to 9.4% for 2 metal-layer layouts and from 6.4% to 12.7% for 3 metal-layer layouts. Finally, a new area estimation model for estimating the layout area of switch blocks in FinFET is introduced in this work. The model not only takes into consideration the active area that is needed to construct a switch block but also the number of metal layers and the dimensions of these metals. We found that the new model improves upon the traditional active-based area estimation models. For the layouts examined in this work, we found that, in the case of metal-dominated layouts, the new area model accurately predicts the layout area of switch blocks, while, in the case of active-dominated layouts, the model predicts the layout area with errors up to 2.5%.