Design of a Low-Power Phase-Frequency Detector and Gain-Boosting Charge Pump for GHz-Range Applications in 180-nm CMOS Technology

Phase-Frequency Detector (PFD) and Charge Pump (CP) are crucial components in Phase-Locked Loops (PLL) and Delay-Locked Loops (DLL), significantly impacting synchronization accuracy and system stability. In this paper, a new PFD based on dynamic logic with a minimal number of devices is designed, providing low delay and proper logic output levels. Additionally, a novel CP employing the gain-boosting technique and utilizing a cascode amplifier is proposed, achieving higher DC-gain and better current matching. The proposed design aims to minimize power consumption to the microwatt level, reduce circuit area, and achieve an operating frequency up to 3 GHz. Simulation results in 180-nm CMOS technology using Cadence software demonstrate that the proposed circuit offers lower power consumption, smaller area, and improved dynamic performance compared to conventional designs, making it well-suited for PLL and DLL applications in high-frequency communication systems.