Integration of ferroelectric memory devices into CMOS circuits

Modern technology faces a memory crisis. As artificial intelligence and smartphones demand ever more data storage and processing power, traditional computer memory is hitting its physical limits. While processors keep getting faster, memory chips struggle to keep up, creating a bottleneck that affects everything from smartphone battery life to training the latest AI models. This research explores a promising solution: ferroelectric memory, a new type of computer memory that could be faster, more energy-efficient, and more reliable than current technologies. This memory "remembers" even when the power is off, making devices more efficient and responsive. However, designing computer chips with this new memory type is like trying to build a house without proper blueprints or building codes—the tools and guidelines simply don't exist yet. This thesis develops those missing tools. By thoroughly testing how ferroelectric memory behaves, creating mathematical models that predict its performance, and designing example circuits that use it, the research establishes a complete design framework. This includes building a digital "twin" of the memory that engineers can use to simulate and optimize circuits before manufacturing expensive prototypes. The work also reveals important trade-offs between performance, reliability, and security that designers must consider. By making these models and tools publicly available, this research provides the foundation for developing next-generation memory systems that could power future smartphones, electric vehicles, medical devices, and AI applications, enabling technologies that are faster, more efficient, and more reliable than what's possible today.