A Novel SRAM In-Memory Computing Accelerator Design Approach with R2R-Ladder for AI Sensors and Eddy Current Testing

This work presents a 6T-SRAM-based in-memory computing (IMC) system fabricated in a 180 nm CMOS technology. A total of 128 integrated polysilicon R2R-DACs for fully analog wordline control and performance analysis are integrated into the system. The proposed architecture enables analog computation directly inside the memory array and introduces a compact 1-bit per-column comparator scheme for energy-efficient classification without requiring ADCs. A dedicated pull-down-dominant SRAM sizing and an analog activation scheme ensure stable analog discharge behavior and precise control of the computation through time-dependent bitline dynamics. The system integrates a complete sensor front-end, which allows real eddy current data to be classified directly on-chip. Measurements demonstrate a performance density of 3.2 TOPS/mm2, a simulated energy efficiency of 45 TOPS/W at 50 MHz, and a measured efficiency of 3.4 TOPS/W at 5 MHz on silicon. The implemented online training mechanism further improves classification accuracy by adapting the SRAM cell states during operation. These results highlight the suitability of the presented IMC architecture for compact, low-power edge intelligence and sensor-driven machine learning applications.