A Whale Optimization-Based Dynamic Compression ATPG Algorithm for Computer Interlocking Equipment Testing

High-speed railway signaling equipment constitutes safety-critical infrastructure, wherein hardware failures may directly compromise operational safety. During the hardware prototyping and verification stage, structural testing is essential to detect latent faults in digital logic circuits and to ensure compliance with stringent safety integrity requirements. However, conventional test generation methods often suffer from long generation times and excessive test vector volume. To address these challenges, this study proposes a whale optimization-based dynamic compression Automatic Test-Pattern Generation (ATPG) algorithm. The proposed method integrates a discrete whale optimization algorithm (WOA) with a deterministic PODEM framework to dynamically compress generated test vectors. Additionally, a multi-path-sensitized PODEM enhanced with desensitization techniques is introduced to reduce backtracking and improve search efficiency. The proposed algorithm has been applied to the computer interlocking golden model netlist for testing purposes, achieving an impressive fault coverage rate of 100%. Test results from the ISCAS-85 standard circuit indicate that our approach significantly reduces both the length of the vector set and the time required for test generation when compared to traditional PODEMs without vector compression and pseudo-random combined PODEM vector generation methods. This advancement effectively enhances overall vector generation efficiency while maintaining comprehensive fault coverage.