FPGA Modular Scalability Framework for Real-Time Noise Reduction in Images

Image noise degrades image quality in applications such as medical imaging, surveillance, and remote sensing, where real-time processing and high accuracy are critical. Software-based denoising can be flexible, but often suffers from latency and low throughput when deployed on embedded or edge systems. A Field Programmable Gate Array (FPGA)-based system offers parallelism and lower latency, but the existing work typically focusses on fixed architectures rather than scalable framework supporting multiple filter models. This paper presents a high-performance, resource-efficient FPGA-based framework for real-time noise reduction. The modular, pipelined architecture integrates median and adaptive filters, managed by a state machine-based control unit to enhance processing efficiency. Implemented on a Cyclone V FPGA using Quartus Prime 22.1std, the system provides scalability through adjustable Random Access Memory (RAM) and supports multiple denoising algorithms. Tested on Leena images with salt-and-pepper noise, it processes 10% noise in 1.724 ms in a simulated environment running at 800 MHz; it was compared with Python version 3.11.2 with the OpenCV-library version 4.8.076 on a general-purpose Central Processing Unit (CPU) (0.0201 ms). The proposed solution demonstrates low latency and high throughput, making it well-suited for embedded and edge computing applications.