Design and Analysis of a Configurable Dual-Path Huffman-Arithmetic Encoder with Frequency-Based Sorting

The designs of lossless data compression architectures create a natural trade-off between throughput, power consumption, and compression efficiency, making it difficult for designers to identify an optimal configuration that satisfies all three criteria. This paper proposes a Configurable Dual-Path Huffman/Arithmetic Encoder (CDP-HAE), which offers an architecture that supports the use of shared preprocessing, parallel path encoding using Huffman and Arithmetic, as well as selectable output. The CDP-HAE’s design prevents the waste of excess bandwidth by sending only one selected bit stream at a time. This also enables adaptation to the dynamically changing statistical characteristics of the input data. CDP-HAE’s architecture underwent ASIC synthesis in 90 nm CMOS technology and is implemented on an Artix-7 (A7-100T) using the Vivado EDA tool, confirming the scalability of the architecture to both devices. Synthesis results show that CDP-HAE improves operating frequency by 28.6% and reduces critical path delay by 27.2% compared to reference designs. Additionally, the dual-path design has a slight increase in area; the area utilization remains within reasonable limits. Power analysis indicates that optimizing logic sharing and minimizing switching activity reduces total power consumption by 34.4%. Compression tests show that the CDP-HAE delivers performance comparable to that of a conventional Huffman Encoder using application-specific datasets. Furthermore, the proposed CDP-HAE achieves performance comparable to conventional Huffman encoders on application-specific datasets, while providing up to 10% improvement in compression ratio over Huffman-only encoding.