A Class-AB Reference Voltage Buffer for SC Circuits in Pipelined ADCs
Abstract
This paper introduces the design of a reference voltage buffer (RVB) for pipelined analog-to-digital converters (ADCs) in a 180 nm CMOS process with a 1.8 V supply voltage. The loop stability of the proposed RVB is verified by the theoretical calculations. The driving capability of the proposed RVB is demonstrated by its large driving current, and the transient response simulation results reveal its impressive speed and precision in the reference voltage settling process. Moreover, the power supply rejection ratio (PSRR) performance indicates that the proposed RVB is insensitive to the variation in power supply voltage, meeting the application requirements for high-speed and high-precision pipelined ADCs.
Fields of Study & Subjects
Analog and Mixed-Signal Circuit Design
Radio Frequency Integrated Circuit Design
Advancements in PLL and VCO Technologies
Publication details
- Journal / source
- Electronics
- Volume
- 15
- Issue
- 3
- Pages
- 547–547
- Publication date
- 27 January 2026
- Language
- EN