The FPGA-Based Control System for High-Speed SRM Drive with a C-Dump Converter

This article focuses on power supply control issues in high-speed switched reluctance motors (SRMs). The primary scientific objective of this study was to determine whether and to what extent, the controller itself imposes limitations on SRM drive operation at very high rotational speeds, and to identify the maximum achievable speed range resulting from these limitations. Unlike most existing studies, which focus mainly on motor or power electronics constraints, this work explicitly analyses the dynamic limitations introduced by the control system architecture. An analysis of the essential controller functionalities required for implementing the SRM drive control algorithm with a C-dump converter was performed. The control system, composed of specialised hardware modules operating concurrently, was implemented in an field-programmable gate array (FPGA) device. Simulation and experimental investigations were conducted to evaluate signal propagation delays within the FPGA and their impact on the motor control process. Key functional modules contributing to the maximum signal propagation delays were identified, enabling a direct determination of the maximum motor speed at which correct power supply operation can be ensured. Furthermore, delays introduced by the power electronic components were characterized for the developed test controller, allowing a comprehensive assessment of both control and hardware-induced speed limitations. The research concluded that the FPGA-based controller introduces no significant limitations to the drive’s maximum speed. The maximum speed is limited by the mechanical constraints of the rotor and the inertia of the phase windings. Furthermore, expanding the controller with additional functionality does not significantly slow down the control algorithm’s execution.