Design and Analysis of FSM-Based AES Encryption on FPGA Versus MATLAB Environment

The present paper compares and analyzes the design of AES-128 encryption and decryption using Finite State Machine (FSM) architecture on FPGA and MATLAB platforms. This study aims to evaluate performance disparities in terms of execution time, throughput, and hardware efficiency under identical input data and key conditions. The FSM-based AES algorithm was modeled in MATLAB for functional validation and synthesized on an Artix-7 FPGA using VHDL. The experimental results confirmed that both platforms produced identical ciphertext and plaintext outputs, verifying the correctness of the processes employed. However, the FPGA demonstrated significantly better performance in terms of execution speed. Encryption and decryption times were measured in microseconds on the FPGA, while similar operations on the MATLAB platform required hundreds of milliseconds. The FPGA implementation achieved throughput of 872.53 Mbps for encryption and 858.49 Mbps for decryption with area usage of 1263 and 1428 slices, respectively. This yields an efficiency of 0.691 and 0.601 Mbps/slice, which is considered efficient according to established benchmarks. Compared to previous MATLAB-only and FPGA pipelined implementations, the current design strikes a balance between resource usage and performance, making it ideal for lightweight cryptographic applications in embedded systems. These results provide practical insights into selecting platforms for secure, real-time data processing.