Empirical Modeling of Current Drawn by High-Speed Circuits for Power Integrity Simulations

Firm requirements on electromagnetic compatibility (EMC) of electronic devices demand low electromagnetic emissions (EMI) of high-speed circuits, especially in the automotive industry. To be able to apply cost-effective anti-perturbative measures that reduce noise emission, critical signal integrity and power integrity (SI/PI) tools are needed for developing high-speed printed circuit board (PCB) designs. This paper presents an efficient method for modeling and analyzing the current drawn by digital ICs based on SPICE modeling data. The profile of the current drawn by the ICs from the power supply is composed of the static supply current and the dynamic supply current. This method enables power integrity engineers, in particular, PhD students and researchers who aim to develop an intuitive understanding of PI phenomena during the pre-layout phase, to see the hidden impact of the supply current on the power rail noise through time domain simulations, using a complex simulation model that integrates the Finite-Difference Time-Domain (FDTD) method of modeling the power and ground plane, with Voltage Regulator Modules (VRMs) and decoupling capacitors. A comparison of simulation results between the proposed models and SPICE IC models is also included to validate the proposed model.