A Multiplier-Free, Electronically Tunable Floating Memtranstor Emulator for Neuromorphic and Artificial Synaptic Applications

This paper presents a compact floating memtranstor (MT) emulator, a memory element characterized by a direct φ–q relationship, realized without analog multipliers or complex circuitry. The proposed design employs only two active blocks—a voltage differential transconductance amplifier (VDTA) and a voltage differential current conveyor (VDCC)—along with three grounded capacitors and a single grounded electronically tunable resistor. The emulator accurately reproduces the fundamental φ–q dynamics, exhibiting origin-crossing pinched hysteresis loops under sinusoidal excitation, and operates at a low supply voltage of ±0.9 V. Electronic tunability is achieved via bias-controlled transconductance modulation, enabling flexible adaptation across excitation frequencies and operating conditions. Validation is performed through analytical modeling, Monte Carlo simulations, temperature sensitivity analysis, and full LTspice post-layout simulations using a 180 nm CMOS process. The full-custom layout occupies 2529.49 μm2, with robust performance confirmed under parasitic and process variations. Adaptive learning simulations demonstrate the emulator’s artificial synaptic plasticity, highlighting its suitability for neuromorphic computing, chaos-based circuits, and nonlinear dynamical systems. The compact, low-power, and multiplier-free architecture establishes the proposed MT emulator as a practical platform for emerging analog memory-centric applications. To validate the feasibility of the proposed solution, experimental tests are performed using commercially available components.