Adjustable ON-TIME Delay TI-ADC via Dual-Slope PWM and Four-Phase Binary Up/Down Counter

Time-interleaved analog-to-digital converters (TI-ADC) are sensitive to inter-phase timing skew, which degrades effective resolution unless mitigated by careful phase alignment or calibration. This paper presents a low-speed proof-of-concept four-phase TI-ADC based on dual-slope pulse-width modulation, incorporating an adjustable ON-TIME delay mechanism at the analog front end. The proposed approach enables controlled shifting of the effective sampling instant at the comparator/D-flip-flop interface without altering waveform amplitude or functional linearity. A four-phase up/down binary counter implemented using a Gray-code-based phase multiplier provides evenly spaced phases with reduced switching activity. Measurements from a breadboard prototype operating at approximately 1.5 MHz demonstrate that the adjustable ON-TIME delay can align adjacent phases and constrain observed inter-phase timing skew to the order of approximately 30 ns within the measurement resolution. The results indicate that analog front-end phase pre-alignment can complement or relax subsequent digital background calibration in time-interleaved ADC systems.