An Optoelectronic CMOS Transimpedance Amplifier Using an FVF-Based Low-Dropout Regulator for PSRR Enhancement

This paper presents a flipped-voltage-follower low-dropout regulator (FVF-LDO) for power supply rejection enhancement and low-power operation in CMOS transimpedance amplifiers for optical receiver applications. The proposed FVF-LDO ensures high stability and reliable regulation over a wide range of load conditions by employing a flipped-voltage follower for fast local feedback and improved power supply rejection, while a super-source follower enhances the transient response through increased current-driving capability. A bandgap reference with a 3-bit trimming DAC is adopted to compensate process variations and support stable LDO operations, achieving a temperature coefficient of 19.6 ppm/°C over a wide range of −25 °C to 125 °C. The FVF-LDO exhibits a 101 mV undershoot under a 100 µA-to-10 mA load step with a 100 ns edge time. When applied to an optoelectronic inverter-based active-feedback transimpedance amplifier (TIA), the regulated supply improves the power supply rejection ratio (PSRR) from −6 dB to −38.3 dB. The proposed optoelectronic TIA realized in a 180 nm CMOS process achieves 67 dBΩ transimpedance gain, 869 MHz bandwidth, 66 dB dynamic range, 6.68 pA/√Hz input-referred noise current spectral density, and 4.68 mW power consumption from a single 1.8 V supply. The proposed TIA chip occupies a core area of 940 × 162 µm2.