A Fully Integrated Gate-Pole-Dominant Low-Dropout Regulator with Loop-Gain Booster for Maintaining High Power-Supply Rejection over a Wide Load Current Range

This paper introduces a fully integrated gate-pole-dominant low-dropout regulator (LDO) that eliminates the need for external capacitors while sustaining high power-supply rejection (PSR) over a broad load current range. A loop-gain booster (LGB) is proposed to maintain the DC operating point of the error amplifier output at its optimal value, thereby preserving a high unity-gain frequency (UGF) even as the load current varies from zero to 200 mA. The parallel signal paths within the LGB inherently produce a left-half-plane (LHP) zero, which cancels one of the poles within the UGF of the feedback loop and guarantees robust stability under diverse operating conditions. Fabricated in a 40 nm CMOS technology, the prototype occupies only 0.008 mm2 with a 4 pF on-chip compensation capacitor. The proposed LDO achieves a PSR of −72 dB at 1 MHz and −40 dB at 10 MHz when IL = 200 mA and VDO = 0.1 V, and maintains a PSR better than −78 dB at 1 MHz and −42 dB at 10 MHz when IL = 1 mA and VDO = 0.1 V. The LGB-enhanced regulator achieves excellent load and line regulation figures of 29 μV/mA and 0.75 mV/V, while the LGB itself consumes merely 7 μA out of a total quiescent current of 108 μA.