Co-Design of Pipelining and Fixed-Point Quantization for SOVA-Turbo Codec IP Core

With the escalating demand for high reliability, low power consumption, and high throughput baseband processing capabilities in 5G and future 6G communication systems, the channel coding and decoding IP core serves as a critical module in baseband chips, where its hardware architecture and numerical system design exert a decisive influence on system performance. This paper proposes a SOVA-Turbo codec IP core architecture tailored for FPGA/SoC system integration. By reconstructing the Turbo iterative decoding data flow, a pipelined architecture is designed to facilitate the parallel operation of component decoders, as well as the storage and distribution of extrinsic information. Furthermore, addressing the numerical complexity of the SOVA algorithm in hardware implementation, a customized fixed-point representation and quantization co-design scheme is proposed to support hardware-efficient implementation while preserving the relative reliability relationships required for soft-decision decoding. Additionally, bit-level soft reliability information is generated at the decoder output to support iterative reliability evaluation under controlled noisy conditions. Simulation and implementation results demonstrate the feasibility of the proposed prototype in terms of timing closure, hardware cost, and decoder-side robustness under controlled perturbation.