Quantifying and Correcting Systemic Offset Errors in PWM and Peak–Valley DC–DC Converters

DC–DC converters are ubiquitous in consumer, industrial, commercial, and medical applications. In such voltage-, power-, and area-constrained systems, guaranteeing accurate output voltage remains a key challenge. Investigation of the fundamental cause of steady-state output errors in DC–DC converters, however, is largely absent in the literature. This work identifies systemic voltage offset error as one of the key contributors to steady-state output inaccuracy in PWM and peak–valley-controlled switched-inductor voltage regulators. It uses an insightful reverse-feedback translation framework to quantify the systemic offset as a function of the duty cycle, input voltage, sawtooth amplitude, propagation delays, load conditions, error amplifiers, and comparator. Furthermore, with the derived offset expressions, the paper develops accurate and low-overhead design guidelines to remove systemic errors by aligning the regulator’s steady-state equilibrium with its operating conditions. With the proposed offset “centering” and “elimination” techniques, the systemic error (that accounts for up to 2.1% variation in the steady-state output) is reduced by over 70% when centered and to zero when eliminated at room temperature. Overall, this work provides an insightful and generalized quantification of systemic offsets and describes low-overhead strategies to restore steady-state accuracy in practical PWM, hysteretic and peak/valley-controlled voltage regulators.