Design and Performance Analysis of Double-Gate TFETs Using High-k Dielectrics and Silicon Thickness Scaling for Low-Power Applications

Tunnel Field-Effect Transistors (TFETs) are being explored for ultra-low-power very-large-scale integrated circuits (VLSI) because their band-to-band tunnelling (BTBT) transport permits subthreshold swings (SS) below the 60 mV/dec thermionic limit at room temperature, along with significantly lower leakage than MOSFETs. This paper presents a systematic TCAD study of DG-TFETs that maps how four primary knobs–gate dielectric materials, silicon channel thickness, temperature variation, and different channel material shape key figures of merit: the ON current (ION), OFF current (IOFF), threshold voltage (VTH), SS, and the ION/IOFF switching ratio. High-k gate enhances gate-to-channel coupling and boost tunnelling efficiency; rigorous body scaling enhances electrostatic control; and targeted source-proximal doping profiles elevate ION while minimizing leakage. We also measure the trade-offs between ION, SS, and IOFF that occur when scaling is performed at the same time. This shows that careful coordination is needed instead of just tuning one parameter. This is a simulated work, and the physical models are calibrated to experimental TFET data and all parameters are checked against previously reported results. The device reaches SS = 31.4 mV/dec, VTH = 0.46 V, ION = 5.91 × 10−5 A and an ION/IOFF of about 4.5 × 1011. This shows that it can switch quickly with little leakage. The design insights that come from this work provide useful advice regarding how to choose gate dielectric material, structures, and doping strategies to add DG-TFETs to the next generation of low-power semiconductor technologies.