Memristor Models with Parasitic Parameters for Analysis of Passive Memory Arrays

Memristors are valuable elements with very good memory and switching features. They have minimal power consumption, nano-scale sizes, and a possibility for integration with high-density Complementary Metal Oxide Semiconductor (CMOS) integrated circuits. They are applicable in neural networks, memory crossbars, and different electronic devices. This work considers some improved and existing models for memristors, functioning at high-frequency signals with a high speed and very good effectiveness. The main parasitic parameters—series resistance, capacitance, and small-signal direct current (DC) voltage and current shifting signals—are taken into account. An additional leakage conductance is analyzed as a parasitic component. The influence of the parasitic parameters on the normal functioning of memristor-based circuits is analyzed and evaluated at hard-switching and soft-switching modes. For investigations of the main characteristics of the considered models and their applicability in memory arrays, Linear Technology Simulation Program with Integrated Circuits Emphasis (LTSPICE) library models are generated and analyzed. The considered models operate at low-, middle- and high-frequency signals, clearly demonstrating the main properties of memristors. Their appropriate operation in passive memory arrays is analyzed and established. The proposed models have a 26% enhanced accuracy in fitting experimental i-v relations. They ensure good memory and switching properties for memory arrays. This work could be a suitable step towards the design and manufacturing of ultra-high-density memristor-based integrated chips.