A CO-OPTIMIZED 12X12 MODIFIED BOOTH MULTIPLIER ARCHITECTURE WITH CUSTOM PARTIAL PRODUCT GENERATOR AND 10 T ARITHMETIC BLOCKS

This paper presents a Modified Booth multiplier architecture based on a cooptimized combination of algorithmic circuit-level, and physical design techniques.A novel partial Product generator is proposed using NMOS Pass-logic and half-adder based two's complement correction, eliminating conventional shifter and signextension hardware.Wiring based shift alignment is employed to map partial products directly into the reduction tree, reducing switching activity and routing overhead.The multiplier further integrates custom 10-transistor adders and 10-transistor D flip flops for pipelined operation.The complete-design is validated through full custom layout, demonstrating significant reductions in transistor count, power consumption, and silicon area compared to conventional Booth Wallace implementations.