IMPLEMENTATION OF PARTIAL PRODUCT GENERATOR FOR LOW POWER LOW AREA COMPLEX MULTIPLIER
Abstract
The design of a partial product generator which is used in modified booth encoder for design of 12x12 complex multiplier is presented in this work.It is designed using less number of transistors to achieve less area and power.Here Partial product generator and Booth encoder circuits are provided.Design of both circuits utilizes circuit optimization technique.Approach used is bottom up.Since a smaller number of transistors are utilized, speed increases, lowers power and area resulting in overall less Silicon area.The design is implemented and verified in cadence and simulated with ADE Spectre simulator for both pre and post layouts using 0.18µm technology.
Fields of Study & Subjects
Low-power high-performance VLSI design
VLSI and FPGA Design Techniques
Analog and Mixed-Signal Circuit Design
Publication details
- Journal / source
- INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY
- Volume
- 17
- Issue
- 1
- Pages
- 1–18
- Publication date
- 27 January 2026