Design of multi-level ReRAM resistance states for Column-wise Weight Value Inversion (Colwin) to reduce MAC error of ReRAM-based analog Computation-in-Memory

Abstract This paper optimizes the design of TaO X -based Multi-Level Cell (MLC) ReRAM resistance states for an error correction scheme called Column-wise Weight Value Inversion (Colwin) to reduce the multiply-accumulate value (MACV) errors in analog ReRAM Computation-in-Memory (CiM). The proposed Colwin reduces MACV errors by inverting the weights of neural networks (NNs) to ReRAM resistance states. ReRAM cell current distributions for each resistance state affect the error correction capability of the proposed Colwin. Therefore, in this paper, 4 design cases of ReRAM resistance states are discussed. This paper indicates that the non-uniform ReRAM cell current distribution design is more effective to improve inference accuracy compared to conventional wide-range uniform design. As a result, the proposed Colwin improves inference accuracy by 39.8% those without the proposed Colwin for DR time equivalent to 12 months at 85 °C. Moreover, the proposed Colwin reduces the overhead of the flag bits by 78.5% compared to conventional error correcting codes (ECC).