Lithography at the end of scaling

Abstract To reach the smallest dimensions projected in current technology roadmaps, full enablement of high-numerical aperture (NA) extreme ultraviolet (EUV) lithography with high levels of productivity will be needed. Issues related to masks, resist materials, EUV light sources, and computational lithography will also need to be addressed. Curvy features offer the potential to increase the performance of integrated circuits while decreasing power consumption. To realize the benefits of backside interconnect, lithographers will need exposure systems and metrology tools that can align wafers and measure overlay through thick layers of silicon. New lithographic capabilities need to be developed for supporting advanced packaging. Should solutions be found that enable smaller transistor or interconnect dimensions than in current roadmaps, there are a number of potential patterning solutions, such as hyper-NA lithography (NA ≥ 0.75) with 13.5 nm wavelength or lithography at a shorter wavelength. Further improvements in productivity and energy efficiency are being pursued, regardless.