Impact of a single interface-trapped charge on threshold voltage variation in gate-all-around nanosheet field-effect-transistors analyzed by 3D TCAD simulation

Abstract The impact of a single interface trapped charge on threshold voltage ( V th ) variation in a gate-all-around (GAA) nanosheet (NS) field effect transistors was evaluated using our custom 3D TCAD simulation framework. While silicon-on-insulator planar structures showed minimum dependence of V th variation on silicon thickness, NS devices showed significantly high sensitivity. In NS architecture, V th variation increased markedly as the silicon layer thickness was scaled down. The primary difference of the NS architecture was the presence of a channel distributed throughout the silicon sheet, enabled by the surrounding gates. At a thickness of 4 nm, the charge-induced potential extended to the counter-surface side, nearly eliminating the carrier path beneath the trapped charge. This impact was comparable to that caused by silicon thickness fluctuations with a few angstroms. These results suggest that in GAA architectures, silicon thickness scaling is a critical factor for evaluating V th variation induced by trapped charges.