Guideline for balancing threshold voltages in gate-all-around CMOS by controlling the thickness of the work function metal under tight nanosheet spacing

Abstract This study demonstrates the feasibility of tuning the symmetric threshold voltage for gate-all-around field-effect transistors (GAAFETs) with a nanosheet-to-nanosheet spacing of less than 10 nm using TiN/TiAlC/TiN gate stacks. Capacitance–voltage measurements using metal-oxide-semiconductor capacitors confirm that the threshold voltage can be modulated effectively by controlling the thickness of the TiAlC layer, and the effective work functions (EWFs) of 4.47 and 4.77 eV are required for n -GAAFETs and p -GAAFETs to achieve a threshold voltage of ±0.2 V at a gate length of 20 nm. High-resolution Rutherford backscattering spectroscopy and ultraviolet photoemission spectroscopy reveal the intrinsic work function of TiAlC, and cross-sectional transmission electron microscopy shows interfacial SiO 2 thinning with thicker TiAlC layers. Direct tunneling simulations reproduce the observed gate-leakage trends, highlighting the role of interface modifications and potential oxygen scavenging. These results establish a scalable approach for precise EWF and leakage control in sub-5 nm gate-thick stacks for GAAFETs.