Polytype evaluation in 3C-SiC/4H-SiC stacked epilayers on trenched 4H-SiC substrates using Raman spectroscopy

Abstract This study investigates the growth of 3C-SiC on 4H-SiC substrates using the simultaneous lateral epitaxy (SLE) method to overcome interface-state and mobility issues found in 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs). Because 3C-SiC wafers are not commercially available, SLE growth on patterned trenches is used to control 3C-SiC nucleation. Raman spectroscopy is employed to evaluate how trench geometry influences the amount of 3C-SiC formed. The results show that deeper trenches increase the exposure of 3C-SiC on the surface, while wave-shaped trench structures limit 3C-SiC nucleation due to limited terrace width. A comparison of two wafers indicates that greater trench depth enhances 3C-SiC content. The findings suggest that optimizing trench depth and wave-like trench structures is essential for promoting 3C-SiC growth while reducing crystal defects such as twin boundaries.