Design–technology co-optimization (DTCO) of inner-spacer length dependence in nanosheet logic transistors using hierarchical performance–power metrics

Abstract We study the role of inner spacer length (L is ) in nanosheet logic using a design–technology co-optimization (DTCO) flow linking device, interconnect, and implementation metrics, emphasizing the coupled impact on device saturation current (I on ), cell parasitic capacitance (C para ), and resistances including contact (R con ) and interconnect (R MOL /R BEOL ). TCAD and compact BSIM-CMG models are calibrated; standard-cell layouts are built for frontside (FS) and backside-contact (BSC) power delivery network (PDN); parasitics and R con are extracted by a field solver. A 15-stage FO1 ring oscillator (RO) provides circuit metrics, and a template generates NAND/NOR cells for a pseudo logic-block gauge of performance, power, power-delay product (PDP), and energy-delay product (EDP). As L is increases, I on and C para decrease while R con increases at larger L is . RO simulations show optimum design window at L is = 6.2–7.6 nm (FS) and 4.0–6.8 nm (BSC). Within the windows, RO EDP is reduced by 14.7% (FS) and 22.4% (BSC) over the baseline. PDP decreases as L is increases since PDP is mainly determined by switched capacitance. Multivariate regression shows MOL capacitance contributes most to EDP variation, followed by I on and R con , while R c on dominates maximum frequency. Pseudo logic-block gauges indicate a flat optimum design window of 5.5–7.6 nm (FS) and 5.0–8.0 nm (BSC) than RO, with EDP improvements of 12.5% and 24.2% over the baseline. This compact framework supports DTCO pathfinding by selecting L is under realistic parasitics and by comparing FS and BSC at circuit and pseudo logic-block levels.