TCAD analysis on defect-induced degradation of electrical and retention characteristics in 3D DRAM

Abstract During the fabrication of dynamic random-access memory (DRAM), silicon nanosheets can bend or shear under mechanical stress, leading to lattice distortions or dislocation that cause reliability issues. This paper investigates dislocation-induced effects in gate-all-around nanosheet-based 3D DRAM using TCAD simulations across four dislocation scenarios: within channel region, spanning from bit line (BL) to storage node (SN), at BL edge, and SN edge. Dislocations in the channel region increase the threshold voltage and subthreshold swing, thereby reducing on-current, leading to slower read-write operation. And dislocation near SN edge significantly increases leakage current through enhanced band-to-band generation due to higher electric field, shortening retention time compared to defect-free device. Additionally, higher-temperature dislocation study reveals electrical characteristics degradation, and the combined effect of interface-trap charge along with dislocation defects causes substantial reduction in retention characteristics of DRAM. These findings highlight the critical reliability concerns and importance of Si-defect mitigation for future DRAM technology.