Microarchitectural Advancements in Branch Prediction: Evaluating Modern Techniques for Out-of-Order RISC-V Processors

Today’s out-of-order processors include branch prediction in their microarchitecture to improve the throughput, execution and performance. The aim of this research paper is to evaluate the advanced branch prediction techniques including TAGE-SC-L, L-TAGE, BiMODE, Tournament Predictors, and Multi-Perspective Perceptrons throughout outof-order RISC-V processor design. We use SPEC CPU 2017 benchmark suite in the gem5 simulation framework to study the accuracy of predictions, mispredictions and execution time for different workloads. One of the first uniform simulation-based studies of traditional and MLbased predictors for RISC-V which illustrates practical trade-offs between power and hardware complexity is the current work. Findings suggest TAGE-SC-L provides an optimal trade-off in accuracy and efficiency enabling improved prediction strategies in systems that are energy-wasteful for best outcomes. Findings can influence the microarchitecture choices of future RISC-V implementations.