A CMOS Measurement-Collapse Primitive for Ephemeral Secrets in Post-Quantum Cryptography

Post-quantum cryptography (PQC) depends on large, short-lived secrets whose lifetime at the hardware boundary must be tightly controlled: even brief residency in conventional volatile memory exposes them to microarchitectural leakage, DMA visibility, speculative execution, and delayed software zeroization. This paper introduces a CMOS-realizable measurement–collapse primitive that enforces read-once semantics at the digital interface: the first authorized architectural read discloses a stored value and, inseparably with that read event in the synthesized design, triggers a deterministic collapse that prevents the value from being re-issued through the modeled interface on any subsequent access. In our FPGA prototype, the DATA register is implemented as a TRIG+READ semantics: any DATA read request is itself the trigger that causes collapse, preventing “probe-before-trigger” firmware behavior at the MMIO boundary. This logical measurement–collapse behavior captures the core semantic requirement for PQC-era ephemeral keying, while recognizing that the underlying storage elements in the present FPGA realization are still conventional CMOS registers; eliminating residual electrical persistence in a fabricated ASIC is explicitly deferred to future work. A 1024-cell FPGA prototype on an Intel Cyclone V validates this behavior for 8+8-bit cells, with per-cell costs of ∼17.09 ALMs and 26.69 registers and single-cycle collapse timing at 50 MHz. Within this prototype, we empirically demonstrate (i) exactly one disclosure per cell (at most one correct-basis disclosure per INIT), (ii) immediate RTL-level invalidation of the stored value, and (iii) no re-issuance of that value under repeated, mismatched-basis, or adversarial Avalon-MM access patterns at the digital boundary. The post-collapse stream is treated solely as an obfuscation mechanism in this work; no entropy, randomness, or NIST SP 800-90B/C certification claims are made for it. We formalize an idealized measurement–collapse model, evaluate a CMOS-realizable primitive that enforces read-once semantics at the architectural interface, and discuss design considerations for a future ASIC realization. While motivated by the requirements of post-quantum cryptography, this work focuses on enforcing ephemeral, single-use behavior at the hardware boundary rather than on full protocol integration. Constant-time hardening, certified entropy evaluation, physical-security characterization against invasive attacks, and demonstration of true electrical non-persistence at the device level are explicitly identified as future work.